In the manufacturing of integrated circuit (IC) chips, a quality control procedure is an important step to insure that the circuits will perform as designed. The quality control procedure involves various steps of testing the major functions of the chip. For instance, tests frequently involved are the short circuit/broken circuit test, a cell function test, and a direct current test. These tests are normally conducted on sophisticated and expensive test equipment and are very time consuming. However, due to the importance of the quality control procedure, they must be performed as part of the IC manufacturing process.
Presently, two test methods are commonly used in the IC manufacturing industry. The first method tests one IC chip on a single test machine at a time. If is therefore a very time consuming process. The second commonly used test method is a parallel testing method which uses a multiple set of address input lines. This method requires the installation of a multiple set of address input lines and therefore requires additional equipment expenditures.
It is therefore an object of the present invention to provide a test method for integrated circuit chips that does not have the shortcomings of the prior art test methods.
It is another object of the present invention to provide a method of testing integrated circuit chips that does not require the installation of a multiple set of address input lines.
It is a further object of the present invention to provide a method of testing integrated circuit chips that is capable of testing multiple IC chips in parallel by a single testing machine.
It is yet another object of the present invention to provide a method of testing integrated circuit chips by first connecting all of the corresponding address input pins of the chips together and then to the address input lines of the testing machine, connecting all the data I/O pins to the data I/O pins of the testing machine, and connecting the voltage input and ground of the chips to separate voltage sources.